Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS

With the advanced scaling of CMOS technology in the nanometer range, highly integrated mixed-signal systems can be designed. The use of nanometer CMOS, however, poses many challenges. This keynote presentation gives an overview of problems due to increased variability and reliability. Both have to be addressed by the designer, either at IC design time or through reconfiguration at IC run time. Design tools for the efficient analysis and identification of reliability problems in analog circuits is described. Also, run-time circuit adaptation techniques are presented that allow a circuit to recover from degradation failures. Georges G.E. GIELEN received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. He currently is a Full Professor at the Katholieke Universiteit Leuven. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixedsignal testing). He has authored five books and more than 300 papers in journals and conference proceedings. He is Fellow of the IEEE and served as the 2005 President of the IEEE Circuits And Systems (CAS) Society.